| For producers, an in-depth and comprehensive study on the FPGA testing techniques is an important prerequisite to ensure the successful manufacture of high reliability chip. So this paper focuses on the test problems of FPGA. Firstly, point out the main problems by analyzing the existing FPGA test methods:1) the test methods based on ATE require expensive auxiliary equipment, and limited by the number of chip package pin;2) the separating test methods based on BIST need plurality programming, it is a long time to finish the complete test. Then a multi-resource joint test method based on BIST is proposed, and its feasibility also be verified. This paper includes the following aspects:1. Consider the problems above, focuses on the smallest same cell in the FPGA internal resources, a new division is proposed to build a set fault models for multi-resource joint test. And then this fault model set is used to test the FPGA programmable logic and interconnect resources.2. A controllable traversal test vectors design method is proposed. It can skip the test vectors do not contribute to the circuit under test under the control of the control code, only to produce the sequence of test vectors to detect the failure of circuit under test, thus achieving the purpose of reducing test times, and reduce the test power consumption.3. An output response analyzer connects closely with BIST controller is designed and implemented. It is completely different from traditional output response analysis and design methods which based on the LFSR. This method requires the same hardware overhead as the traditional method, while the proposed method can not only detect faults but also diagnose the fault.4. Based on above, a multi-resource joint BIST test method is built. The actual verification indicates:this method can reach100%fault coverage in the cases of The connection channel open/short faults and delay fault, the programming switch stuck on/off faults and the LUT stuck-at0/1faults. |
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