Design and implementation of a novel BIST scheme for Xilinx XC4000E FPGAs

This thesis presents novel built-in self-test (BIST) schemes for testing configurable logic blocks (CLBs) and interconnect in Xilinx XC4000E SRAM-based field programmable gate arrays (FPGAs). The minimum number of test configurations for CLBs and interconnect are derived.; The proposed BIST scheme for CLBs includes the testing of FPGA carry logic modules (CLMs) for the first time. A systematic method is proposed for deriving the minimum number of testing configurations for CLMs, and the testing for the remaining CLB resources is integrated with the CLM test configurations.; One novel technique, functional test of D flip-flops, is proposed in the BIST scheme for the sequential part of FPGA interconnect. It can be combined with another novel technique from Dr. Sun, error-control coding for the combinational part of FPGA interconnect, to provide superior multiple fault coverage in FPGA interconnect testing.; A design flow developed by Susan Xu and others is used in this project with some modifications to implement the proposed test configurations. Simulation results are provided to demonstrate the feasibility of the proposed BIST scheme.