A Design Of Embedded Flash Memory’s BIST Circuit

Numerous SoC(System on Chip) integrate FLASH memories, and the memory capacitance are increasing continually. This trend issues many difficulties to test the chips. Although many algorithms for testing embedded memories have already been published, owing to the long period of erase/program FLASH, there are still some improvements to make.This study is trying to design a BIST circuit, which can optionally execute MSCAN, checkerboard and GALDIA algorithms. To save the I/O of the chip, the circuit converts serial data to parallel data.This paper describes the test theories and methods firstly, then introduces the features of memory testing and fault models. The following chapters describe the mechanism of the erase/program FLASH and introduce the features of the FLASH which is under test. Then the details of this design process are presented. Finally the verilog code is verified by simulation then is released to the user.