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MUX IC Design For Optic-Fiber Communication

Posted on:2006-11-08Degree:MasterType:Thesis
Country:ChinaCandidate:C A ZhangFull Text:PDF
GTID:2178360212982507Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
With the development of information technology, our society is entering information society. Optical-fiber communication system is the principal part of modern information super-highway for its merits such as great capacity, long transmit distance, good anti-interference performance etc.In optical-fiber communication system, MUX (Multiplexer) also named parallel-to-serial converter is one of the key function modules in the transmit part. Its function is to convert multiple parallel low-speed data flow into one serial high-speed signal. The high-peed electric signal is converted to optic signal when it goes through the driver and the laser diode, and the optic signal is transmitted to the receive part though the optic-fiber. Under the rules of Synchronous Digital Hierarchy, the bit rates of MUX are all upper Gb/s at present. In the past decades, these high-speed Multiplexers were realized with GaAs, Bipolar Si and BiCMOS processes. With the scaling down of feature size, it is possible to realize Gb/s ICs by CMOS. This paper presents the design procedure of a 0.25μm CMOS 16:1 MUX.There are three basic structures of MUX: serial-type, parallel-type and tree-type. Serial type MUX shows small scale, easy clock, but high power consumption. Parallel MUX has the features of small scale, but difficult clock. Tree one has the merits of easy clock and possibility of multi-channel multiplexing, although its scale is large. This paper uses tree-type to realize the 16:1 MUX.Generally, the input clock frequency of MUX is very high, and it is remarkable to decrease the frequency by PLL based frequency synthesizer. Then this paper presents the research and design work done on the frequency synthesizer which can be used in 16:1 MUX.In this paper, the MUX design procedure is presented with the order of system design, circuit design, layout design and test results. The on-wafer test and packaged test results demonstrate that the Multiplexer can work stably at 2.5Gb/s and its power consumption is lower than 0.2W with 2.5V voltage supplement.
Keywords/Search Tags:SDH/SONET, Optic-fiber Communication, Multiplexer, CMOS, PLL, Frequency Synthesizer, VCO, PD
PDF Full Text Request
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