Research And Design Of UWB Frequency Synthesizer

With the development of wireless communication technology, availableresources have become more and more limited. An ultra-wideband (UWB) sustemwith high channel capacity is an attractive solution for the short-range wirelesscommunication system. So studying and improving the performance of UWB circuitsis very important to the development of wireless communication. Among the differentoptions of efficient use of the UWB spectrum, the multi-band orthogonalfrequency-division multiplexing (MB-OFDM) approach has received strong supportfrom several industrial organizations.UWB frequency synthesizer is a key modulewhen designing a MB-OFDM UWB system.In order to accomplish high quality communication, the frequency synthesizer isa key part of the MB-OFDM UWB system. This paper takes UWB frequencysynthesizer as research subjects. A novel frequency synthesizer for UWB transceiversis proposed, based on the systematic analysis of the technological study situation athome and abroad of the UWB frequency synthesizer. The main achievements of thiswork consist of following aspects:(1)Based on the research of the UWB frequency synthesizer, the main indexes ofthe frequency synthesizer are fixed.(2)A high sideband-suppressed frequency synthesizer for14-band MB-OFDMUWB transceivers proposed is based on traditional structure. The proposed frequencysynthesizer only used a PLL、two multiplexer(MUX) and two SSB mixer.(3)In this brief, many circuits were proposed to gain a low cost and highsideband-suppressed frequency synthesizer. First, a two output MUX is employed tosimplify the synthesizer implementation. Second, a SSB mixer with negative-gmcrosscoupled pair and a Q-enhancement LC band-pass buffer circuit are adopted to reducethe sideband-suppressed. Last, a buffer circuit including a differential pair and anegative-gmcross coupled pair is adopted to reduce the spur of the output signals.(4)The frenquency synthesizer is implemented in TSMC0.18-μm RF CMOStechnology。 And ADS is employed to accomplish the simulation, Virtuoso LayoutEditor to finish the layout design. Simulation results show that the sideband rejectionsare all larger than35dBc；The phase noise of the VCO is-99.5dBc/Hz at1MHz offset;The switching time is less than5ns and the active area is1.5*1.4mm2.