0.8V 8bit 50MS/S CMOS D/A Converter And Its Key Techniques

DAC is one of the widely used crucial components in communication systems and process systems for audio and video. Because of the requirements for improving the speed and precision of signal process, so the DAC has to have higher speed and precision, so DAC has become the bottleneck of the system design. In recent years, with the rapid development of mobile electrical devices and systems like notebook computers and cell phones, so the DAC used in mobile devices must have low power. Considering the requirements above, the DAC with high speed, high precision and low power is needed. The approach of low voltage can not only reduce the power of the chip, but also reduce the bandwidth. So the purpose of low power DAC design is to balance the conflict between the power and performance. The design of 0.8V 8 bit 50MS/S CMOS DAC is discussed in this paper in detail.The development of DAC at home and abroad is briefly introduced at the beginning of this paper. We studied the basic principles and structures, and analyze some typical DAC structure in detail. After compared some structures of DAC, the segmented architecture of current-steering DAC is adopted. The 5 MSBS are thermometer code weighed and the 3 LSBS are binary-weighted.A CMOS bandgap voltage reference with low voltage based on the bulk driven technology is designed in this paper, with circuit to improve PSRR and start-up circuit. The simulation result shows that the circuit not only has good temperature coefficient, but also high PSRR, which meet the requirements of the design of DAC mentioned in this paper. The design of circuits of Voltage-Current transition and switch are implemented.With system structure and basic unit circuit designed in this paper, the sampling frequency of DAC can reach 50MS/S. The structure of current-steering can markedly reduce the area and power of the chip.