.8-bit 1-ghz Current-driven Dac Design

With the development of new semiconductor and digital communication technology, large numbers of advanced electronic products appear endlessly in industry of all kinds. Among these techniques and products, data converter is an indispensable and important building block. It functions as providing the necessary conversion between signals encoding information in bits (digital signals) and signals encoding information in amplitude (analog signals). This thesis is to discuss the implementation of DAC.With the problems such as operation frequency, data throughput increasing, system reliability and stability, as well as the intense competition among different industry having been more and more important, DAC circuit must own the characteristics of high speed, high resolution, low power and small die size, etc. This requirement has become one of mixed-signal circuit design bottlenecks of modern communication system.The aim of this thesis is to design a high speed current-steering DAC (CSDAC) according to the characteristics of communication system. In the beginning, a brief introduction of basic concepts and categorization as well as merits and demerits of each kind of DAC is given. Meanwhile, the segmented current-steering architecture is selected for the designated DAC. After that, the properties and causes of forming errors as well as reasonable solutions are analyzed and delivered. Finally, schematic and layout design are discussed and circuit simulation results are provided. This design uses SMIC 0.13μm Mixed Signal 1.3V process.