Study On Design Of High Speed CMOS ADC

With the development of modern digital communication systems, high-speed digital processing system creates a great demand for high conversion rate between analog signal and digital signal, and high-speed ADC has gained a lot of importance and interest.Based on the analysis of characteristics of different high-speed CMOS ADC architectures, this paper studies the various aspects of modern ADC issues such as the principle of sample and hold, the charge injection into the channel of sampling switch, clock feed through as well as other nonidealities. Using TSMC 0.25 microns standard CMOS process, a fully differential SC S/H circuit which is used in a 10bit 50MHz pipeline ADC is designed. The bottom sampling technique is adopted in this S/H circuit. Simulation is performed in Cadence by using spectre. The input range is 2V, the settling time is 3.3ns. Simulation result shows that the nonidealities can be eliminated. The proposed S/H circuit uses folded cascode scheme with gain boosting technique. This architecture can boost the open-loop gain and improve the stability issue. The main opamp uses SC CMFB to stable the DC level while the auxiliary opamps use single output without CMFB to save area. The result shows that under single source power, the open-loop gain of opamp is 93.5dB, unity gain frequency is 241MHz, and the phase margin is 68 degree, which can fully satisfy the specification. Still, the dynamic comparator in pipeline ADC, clock generator, digital calibration circuit and some principle of layout are also discussed and analyzed in this paper...