An All-Digital Phase-Locked Loop IP Core For System-On-Chip

Because the demands of high performance and low cost are now the main challenges for SoC design, the design of phase-locked loops (PLLs) used as clock generators on chip becomes very critical. Traditional PLLs, such as charge-pump PLLs, are mixed-signal circuits, and there are problems when they are integrated with digital circuits. So it is very important to design an all-digital phase-locked loop which is with high performance and compatible with digital circuits.An all-digital phase-locked loop IP core used in the embedded system chip GarfieldⅤwas designed in this paper. Based on the analysis of application requirements of PLL IP core in GarfieldⅤ, the structure and the performance specifications were defined, and the system model was set up. Then the subcircuits were designed. Due to the affection on capture range, power and jitter performance of PLL, the digital controlled oscillator (DCO) was full-custom designed. Other blocks were described by Verilog HDL. By using the physical design flow of DC+Astro+Calibre, the design demand was met and the design time was decreased. At last, the simulation and test was accomplished, and the timing model, function model and physical model were set up to realize a reusable IP core. Due to the reference of the typical design flow of ASIC design, all of the circuits are realized by standard cells, so the ADPLL is fully compatible with digital circuits, and it is easy to implement using any COMS technology and can radically decrease time-to-market for a design.Implemented in SMIC 0.18um CMOS process with 1.8V supply voltage, the area is 252μm×182μm. According to Hsim simulation results, the power dissipation is 3.3mW when the output of the DCO is 250MHz, and the lock time is 9.8us. According to the measure results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 220ps when the DCO output is 188MHz, and can supply clocks for 32 bits RISC microprocessors.