Design Of The All Digital Phase Locked Loop In 0.18μm CMOS Technology

Phase-locked loop (PLL) has obtained the extremely widespread application in many areas, such as analog and digital communication, radio electronics and other fields. Especially the digital modulation demodulation and phase synchronization of communication usually adopted in a variety of phase-locked loop. Compared with the traditional phase-locked loop, all digital phase-locked loop has a number of other attractive features, including highly portable from one process to another,higher noise immunity, better testability, programmability, and ease of integration into digital systems. So researching a kind of phase-locked loop with good frequency stability, strong anti-interference ability and good synchronization performance has very important significance.Based on the TSMC 0.18-μm CMOS technology, an all-digital phase-locked loop(ADPLL) is designed. This ADPLL can be used as clock generator embedded in SOC system. It consists of four major blocks, namely the phase detector(PD), the phase locking controller, the digitally controlled oscillator(DCO), and the programmable frequency divider. The reference clock is provided by SOC, as a general, be a few MHz. In integer-N ADPLL, the frequency of the output clock signal generated by the DCO is divided by N times to produce a divided clock signal. The parameter N will be referred to as the frequency multiplicative factor in the sequel. When the frequency of an ADPLL is locked, the output clock frequency is N times the reference clock frequency. Thus, one can control the frequency of the output clock of an ADPLL by changing this factor. In circuit design, the full custom differential structure of almost zero dead-zone phase discriminator and ring structure of high precision digital control oscillator are adopted. The third-order locking algorithm is adopted for frequency locking and jitter decreasing. Firstly, the frequency is primary locked by the binary search scheme. Then, the phase is locked quickly through a predictive phase-locking scheme. Finally, the jitter is further reduced by a suppressive digital loop filter.The post-simulation results show that the proposed ADPLL can generate the clock with frequency range from 168MHz to 516MHz. When the ADPLL operates at 200MHz, the peak-to-peak jitter is 254ps, and the lock-in time is 27.7μs. The chip area is 0.18mm2, and average power consumption is 2.9mW. This ADPLL system functions well and it is with good characteristic.