The Design Of Cache And MMU Macro Cell

The most difficulty of today's SoC design is the large difference between the low speed of external memory's access and the high speed of the embedded processor. The difference limits the performance of the embedded processor. In the recent years, the difference is becoming larger and larger, as it is called"Memory Gap"by the engineer. Recently, there are a lot of methods to reduce the speed gap, one of the most effective method is to integrate the Cache and MMU module onto the SoC chip. As a result, design a Cache and MMU module with high performance is very important.This paper takes the Garfield5 system chip as research object, which is design by ASIC research center in Southeast University, the main task is to design Cache and MMU module based on the ARM7TDMI core in the chip. Beginning from the introduction of module's principle, we fully consider the effect of area and power, and the application requirement of the system chip to define the design factor and circuit structure. Then we complete the design of the macro module and the control logic of the module. At last the simulation and test work is performed.We use full custom method to design the macro module, especially to the SRAM memory cell. It is because the spending of area and power of the SRAM memory cell takes a lot of pecentage of the whole macro modules'. Using theαexponent MOSFET model to result the word line,bit line power model and delay model, together with the area model and analysis of the read/write reliability, we bring out a method to optimize the memory cell and evaluate the peformance of the result. The optimized cell has not only reduced the power,delay and area, but also strengthened the antinoise ability.Implemented in SMIC 0.18μm CMOS process with 1.8V supply voltage, the area of the module is 3.12mm2(together with the ARM7TDMI core), CPI is 1.19, power is 33.2mW(under 120 MHz's CPU frequency). The MPW result shows that: the Cache and MMU module have good function, but the CPU frequance can only reach 100MHz, we analysis the reson in detail, and bring out a resolve method.