The DFT And Test Generation Of Garfield

As size of system-on-a-chip (SOC) keeps on increasing, design for testability (DFT) has become animportant part of ASIC flow. At the same time, complexity of SOC is a real challenge to DFT and testpattern generation (TPG). In this paper, the research focuses on the implementation of DFT and TPG on aSOCnamedGarfielddesignedinNationalASICCenter.After briefly introducing some aspects related to the test development of Garfield, the paper focuseson the DFTrealization of the chip. For random logic, scan method is adopted. In RTLlevel, DFT aims athow to control clocks and resets. Problems of shift and capture of scan data are considered during scanchain insertion. Good test coverage (98.06%) of stuck-at faults is achieved after implementing full scandesign. Because of the impact on performance and area of the chip due to full scan design, a partial scanflip-flop selection methodologyaiming at the design with hierarchical structure is presented. Experimentalresultsshowtheeffectivenessoftheapproaches.AfterpartialscandesignofGarfieldisfinished,highfaultcoverage(95.60%)ismaintainedwhiletheimpact(only1.80%) ontheperformanceofthechipduetoscandesign is greatly reduced. Built-in self-test (BIST) technique is used in testing embedded SRAM. Fourdifferent March Algorithms which cover most faultsoccurred in SRAMcan be realized with BISTcircuit.SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT. AfterDFT is completed, test patterns are generated for random logic aiming at three different fault modelsincludingstuck-at,transitionandpathdelay,scanvectorsprovidehighfaultcoverage(96.16%,92.26%and11.96%).Statictiminganalysisanddynamicsimulationensurethevalidationofthetestvectors.At the last of the paper, a summary is given and some problems are pointed out.The paper also putsforwardtheresearchaspectinthefuture.