Research And Implementation Of Design-For-Test And On-Chip-Debug Of Embedded Processor

Along with the development of the micro-electronic technology, the semiconductor manufacture craft is getting finer, and the chip scale unceasingly increased. Faults appeared during chip manufacture are increasing variedly. It's more difficult to detect the faults caused by chip design and manufacture. Desing-For-Test technology became one of the factors which chip designers should consider as soon as possible and should remember all through the entire process.Because the system resources of the embedded processor are limited, it can not complete the development and debugging of the application independently. Since the embedded application is widely and deeply approved, the complexity of embedded applications increased. With the increasing of the embedded processors' scale, their performance grows very fast. Also the embedded operation system is widely used. All these facts brought the enormous challenge to the debug techniques of the embedded system. With the features of the high efficiency of debug support, the perfect protection of the target localization during debugging and the support of embedded operation systems and real-time applications, the On-Chip-Debug techniques became one of the key features of an embedded processor.The 32-bit embedded processor EStar is a high performance and low power embedded processor, designed by the EStar Design Group of the Computer School of National University of Defense Technology. It is a successful proceeding on the high performance and low power 32-bit embedded processor design in the Computer School. The author was luckily in the EStar Design Group. This paper based on the Design-For-Test and On-Chip-Debug technical needs of the EStar processor, the main work and the main research achievement of this paper is as follows:Proposed the method of independent designing scan cell and scan chain manually inserting. Designed and implemented the boundary scan test logic of the EStar processor. This method highly approved the flexibility of the design, and supported the conformity of the debug and test interface very well. Also designed the test system based on the JTAG interface of the EStar processor. The test system integrated the internal scan test and memory build-in self-test functions. It much reduced the chip pin increasing caused by test logic, finally decreased the area of the chip effectively.Designed and implemented the On-Chip-Debug function logic based on the JTAG interface of EStar processor. Implemented the high efficiency debug communication and control channel through scan chain structure. Implemented the basic debugging characteristics through the control of the pipeline, such as the single step, the breakpoint, the watchpoint,etc. Proposed an accessing mechanism of the address space. This mechanism is suitable in the SoC platform based on EStar processor, and it has very good compatibility. The On-Chip-Debug system supported the application developing of the EStar processor effectively.Embedded application development and debugging environment is a remote cross-debug software based on the debug support of the embedded processor. It is a necessity in the developing of embedded application. This paper analysises several common embedded...