New built-in self test methods for scan designs

We address several issues related to built-in self test (BIST) for scan designs: test point insertion, power consumption in test mode, design of test pattern generators for scan designs and BIST for delay fault testing.; First we develop efficient and effective test point selection algorithms. We introduce use of memory efficient surrogate fault lists and develop accurate probabilistic surrogate fault propagation methods for the selection of observation test points. We also develop run-time efficient methods for identification and evaluation of high quality control test point candidates. A deterministic method based on logic implications is also introduced to identify synergistic control points.; Next, we focus on power consumption in BIST. Our research particularly targets reduction in peak power consumption. We propose a scan chain disabling methodology for pseudo-random testing of circuits. Scan chain disabling effectively partitions the circuit in test mode and confines the switching activity within a portion of the circuit. Therefore, the peak and the average power consumptions are considerably reduced in test mode.; We also propose a new pseudo-random test pattern generator for scan BIST based on Markov sources. Our method determines the input weight requirements of the circuit using a deterministic test set and maps the spatial correlations between the circuit inputs into temporal dependencies of the bit stream generated by the generator, without explicitly encoding any deterministic test vector. By iteratively modifying the generator behavior in consecutive test phases, we produce bit sequences that are optimal for the remaining fault and achieve full stuck-at fault coverage for various benchmark circuits.; Finally, we develop a BIST test application scheme for transition delay faults in scan designs. We use circuit's own response to first test pattern as the second test pattern to simplify test generation and application. Furthermore, we use more than two functional clock cycles as opposed to using only two functional clock cycles in standard test application schemes. This approach increases the proportion of at-speed tests applied to the circuit for a fixed number of test clocks. As a result, a higher fault coverage can be achieved.