The ASIC Design Of 10gbit/s Ethernet Physical Coding Subsystem Circuit

IEEE has brought out 802.3ae protocol for 10Gigabit Ethernet, and it will be main technology in net science in the future. 10Gigabit Ethernet (10 GBASE-R and 10 GBASE-W) uses 64B/66B coding and decoding, which is the code format transform without the high transition density and its redundancy is small at the cost of complicated synchronization and the storage. Thus scramble is added to the 64B/66B and descramble is otherwise added before the 64B/66B decode.Standard Cell and top-down based design methodology is the most popular in ASIC (Application Specific Intergated Circuit) design. It begins from descripting circuit with hardware description language(HDL), include simulation, logic synthesis, auto-place & route(AP&R), and static timing analysis(STA). A circuit design was designed in this methodology and it based on ARTISAN's TSMC 0.18um Process 1.8-Volt SAGE Standard Cell library.64B/66B coding function module is analysed in this paper. We also discussed entire ASIC design flow. Some inner logic circuit modules such as 64B/66B encode and decode circuit, scrambler circuit and descrambler circuit in the coding module were presented detailedly. Particularly, we put forward a novel asynchronous FIFO circuit structure(gearbox).All logic circuit was simulated by VCS and modelsim simulator and the simulation result showed it realized the function of 64B/66B Coding Logic circuit.