The Circuit Design Of 10gbit/s And Gigabit/s Ethernet Physical Coding Subsystem

This paper is involved in the characteristic of the 8B/10B code, based upon which we advance two methods of coding and decoding. One is the logic relationship to be found out between 8B and 10B, the other is in parallel, the way 8B are coded into 10B or 10B into 8B.In comparison, we find that the latter is better in that its logic is simpler and its structure is compacted with the small numbers of fan-in and fan-out than the former, thus it is beneficial to be integrated in a chip. The results shows that the speed is high, for instance, the circuit can work at least 300Mb/s in TSMC 0.25um CMOS technology. However, the circuit is taped out in TSMC 0.18um CMOS technology. 8B/10B is adopted because the codes have the characteristic of high transition density of 3-8 transitions per 10-bit code-group, which is good to the recovery of the clock in the receiver. 8B/10B is widely used in Gigabit Ethernet, 10 Gigabit Ethernet (10 GBASE-x), VSR, optical communication system and the backboard of the optical communication system.On the other hand, 8B/10B has the high redundancy, which is used for the following: to make error detection more reliable, to separate code-groups for data and control, to provide sufficient transition density for clock recovery, to allow simple code-group synchronization, and to combat poor channel characteristics. So 10 Gigabit Ethernet (10 GBASE-R and 10 GBASE-W) uses 64B/66B coding and decoding, which is the code transform per se without the high transition density and its redundancy is small at the cost of complicated synchronization and the storage, different from 8B/10B. Thus scramble is added to the 64B/66B and descramble is otherwise added before the 64B/66B. The circuit is designed in TSMC 0.18um CMOS technology and taped out in the MPW project.The two chips mentioned above are packaged resulted from a great many inputs and outputs, afterwards the packaged chips are fixed in PCB to be tested.