Digital Audio Wireless Transmission System In The Forward Error Correction Circuits, And Hardware Verification Platform Design And Realization

This thesis presents a Forward Error Correction (FEC) algorithm and its circuit implementation, which is used in the wireless digital audio transmission system. Also, an entire demo platform is built and error-correction ability of the system is tested based on this platform. The results show that, when the BER of the transmission channel is 3×10^-3, after the error correcting of the FEC system, BER is reduced to 10^-7 .In the FEC part, RS(Reed-Solomon) Code and Interleave are chosen as the basic elements of the Error Correction system at first; then the coding parameter and data structure are determined based on the results of Matlab simulation; At last, HDL modules are implemented in FPGA using Verilog HDL, test results and simulation diagrams are presented as well. In the designing process, the proper division of the modules and the cooperation between modules need a lot of consideration, and the Top-Down method is adopted to solve these questions. Interface signals are defined to help communication between modules, and state machines are used within a single module. During code constructing, much attention is paid to the resource spent and concurrent executable ability of the HDL modules. The modules are also designed in the hardware working way, so a high speed with a low hardware cost can be achieved.In the part of platform designing, proper peripheral chips are chosen according to the audio signal format. And how to achieve channel synchronization in the receiving part is an important aspect of wireless transmission system. In order to solve this problem, three algorithms are used; those are Scramble/Descramble, improved Over-sampling, and Frame Synchronization Protocol. This thesis also gives a lot of explanation about these peripheral circuits and related algorithms.