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A 2.5 Gb/s CMOS 1:16 Demultiplexer

Posted on:2007-05-09Degree:MasterType:Thesis
Country:ChinaCandidate:H T XiaFull Text:PDF
GTID:2178360212965043Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Optic-fiber communication network is the principal of current information society. During the last twenty years or more, the optic-fiber communication and related technology progressed innovatively, and the establishment of SONET and SDH made it easy to build optic-fiber communication systems significantly. Most of the optic-networks work at a speed of 2.5 Gb/s, while some of them even 10 Gb/s, and some faster ones are being researched.Optic-fiber communication networks are composed of electronic devices, optic-electronic devices and fibers, whose theoretical speed is Tb/s (1012b/s). The key to determine the system speed is the performance of optic-electronic devices and integrated circuits.The bandwidth and speed of the current fibers is very large while a single way of digital signals is relatively low. One of the most important technologies to increase the speed is to combine multiple narrow band or low rate signal channels into a high rate one. The related technique is called multiplexing. On the side of receiver, the data stream should be recovered to the original low speed. The related technique is called demultiplexing. This function is realized by the circuits called demultiplexer, one of the most important parts either.The 1:16 Demultiplexer proposed in this paper divides one channel of STM-16 high speed signal into 16 channels of STM-1 low speed signals, which are widely used in the various high speed optic communication systems.This design adopts a tree-type structure with cells of 1:2 dividers. The Source Coupled FET Logic is used in the high-speed part of the circuit to achieve the high data rate, and in the low-speed part of the circuit we choose the pseudo-static logic to meet the need of area and power consumption. The chip is fabricated in a TSMC 0.25μm CMOS Mixed-Signal process. A measured data speed of 2.5 Gb/s has been reached with 2.5V power supply. The power consumption is 280mW and the chip area is 1.59mm×1.52mm. This chip can work at the highest rate of 2.8 Gb/s.
Keywords/Search Tags:1 Demultiplexer, optic-receiver, flip-flop, latch, SCFL
PDF Full Text Request
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