Research On Ultra High Speed Demultiplexer IC For Optical Communication Based On GaAs Technique

To satisfy the bandwidth demands of digital communications, speed requirements for telecommunication systems are continually increasing. The current 10Gb/s system cannot fulfill the need of future digital communications, so it's urgent to develop 40Gb/s ICs for the next generation of optic-fiber communications.In this paper, different structures of demultiplexers (Demux) were analyzed and compared in detail. Then, a novel high speed 1:4 Demux, which had the features of simple structure and low power consumption, was presented (patent pending). A 40Gb/s 1:4 Demux was designed and fabricated in the 0.2μm GaAs PHEMT of OMMIC in France and measured successfully.It will be shown that the high frequency performance of conventional CML circuits can be improved by using on-chip inductors. For circuits which can process broadband data signals a circuit technique called shunt inductive peaking can be used to improve the bandwidth by about 70%, and the adoption of the push-pull ac-coupled source follower extends the bandwidth further. By evaluating the self-resonant frequency of a static frequency divider (TFF), the optimization procedure of the MSDFF (Master-Slave D-type Flip-Flop) is simplified。To reduce the cost, simplify the structure and decrease the risk of failure, the frequency divider and 1:2 Demux were designed, fabricated and measured firstly. The highest measured dividing frequency was 27.5GHz and the RMS-jitter of the output waveform was about 800fs. The operation rang of the 1:2 Demux was 0.5 to 24 Gb/s, and the highest and lowest bit-rate is limited by the available differential clock. The chip can even operate with a 40 Gb/s 231-1 PRBS input data and a 10 GHz sinusoidal clock signal which will just output the odd or even data of the inputs. These two sub-circuits can be used in future design without revising.After solving a serial of difficulties, for example the long distance transmission line, the novel 1:4 Demux was designed, fabricated and measured successfully. The maximum and minimum operation speed was 38 Gb/s and 43 Gb/s respectively, and they are limited by the measurement equipment. The measurement result verified that the design methods were practicable and helpful to future optical transceiver IC design. A 40 GHz dynamic frequency divider was designed additionally because not all of the front circuits (Clock Recovery Circuits) could offer an half rate clock signal.