Design Of Low Power And High Performance Flip-flops Based On CNTFET

Nowadays,various portable electronic products are very fashionable,and these products have high requirements for endurance.In addition,in some specific environments(such as aerospace,and automotive chips),the chip’s anti-interference ability is required to be relatively high.These factors promote the development of low-power and high-performance,high-reliability chip designs.The power consumption of the clock network accounts for a large percentage of the total power consumption of the chip,and the flip-flop is an essential part of the clock network,which affects the chip’s performance.Therefore,the design of low-power and high-performance flip-flops is an essential part of the overall chip system design.The feature size of silicon-based MOSFET has approached the physical limit with the development of Moore’s law.Researchers have to start looking for new materials to replace silicon-based MOSFETs.CNTFETs are considered as the most promising alternative to silicon-based MOSFETs because of their low power consumption,high speed,and high reliability.To promote the development and application of CNTFET technology,this paper focuses on the design of low-power,high-performance flip-flops based on CNTFETs.The specific contents are as follows:(1)To address the level conversion problem inside the chip,this paper firstly proposes a novel double-edge clock pulse generator,and based on this,We further proposes a novel CNTFET pulsed level converting flip-flop named DBS-LCFFCC using conditional charging technique,and a novel CNTFET pulsed level converting flip-flop named DBS-LCFFP using the pre-charging technique.(2)To address the soft error problem caused by the single event effect in digital circuits,this paper firstly proposes a novel dual-node self-recoverable hardened cell named DNSR-DICE,and based on interlocking three DNSR-DICE cells,we propose a novel triple-node-upset self-recoverable latch called HLTNURL,which can effectively solve the soft errors caused by the single event effect.(3)To optimize the performance of the two designed CNTFET level-shifting flip-flops,this paper firstly investigates the effects of parameters such as the number,diameter,and spacing value of carbon nanotubes on the output characteristics and transfer characteristics of CNTFETs.On this basis,the optimization method of the CNTFET flip-flop circuit is proposed.The above research contents are simulated and analyzed by HSPICE software.The specific results are as follows :Under the same process conditions and switching transition chances,the PDP of the designed DBS-LCFFCC is reduced by 19.2%～67.2%,while the PDP of the DBS-LCFFP is reduced by 41.6%～76.3% compared with the existing level-shifting flip-flops.In addition,DBS-LCFFCC has lower power consumption and is more suitable for low-power design,while DBS-LCFFP has a lower delay and is more suitable for high-speed circuit design.The experimental results show that under any PVT variations conditions,the power consumption of DBS-LCFFCC is the smallest,while the delay of DBS-LFCFFP is the lowest,indicating that they are more robust.The simulation results under different processes show that DBS-LCFFCC and DBS-LCFFP under the CNTFET process consume less power and delay.Under the same experimental conditions,compared with the existing triple-node-upset self-recoverable latch,the proposed HLTNURL has an average power consumption reduction of 32.51%,an average delay reduction of 79.73%,an average area reduction of 1.32%,an average APDP reduction of 88.37%,indicating that HLTNURL is suitable for low-power and high-performance design.In addition,HLTNURL is insensitive to PVT fluctuations and is more suitable for digital circuit design with high-reliability requirements.The simulation results under different processes show that HLTNURL under the CNTFET process has lower power consumption and delay.Using the optimization method of the CNTFET flip-flop circuit proposed in this paper,the two proposed CNTFET-level conversion flip-flops are optimized.The simulation results show that the power consumption of the optimized DBS-LCFFCC is reduced by 13.07%,the delay is reduced by 20.06%,the PDP is reduced by 30.5%,and the power consumption of the optimized DBS-LFCFFP is reduced by 14.29%,the delay is reduced by 19.46%,and the PDP is reduced by 30.97%,indicating that the proposed optimization method of the CNTFET flip-flop circuit is feasible.