A 0.25μm CMOS 1:16 Demultiplexer

With the progress of science , communication technology is changing quickly as one of the primary method of modern science. Currently, the network multimedia service is developing rapidly .Such new services as VOD ,network meeting, video telephone and etc. need faster data transmission rate. Therefore the requirement of ultrahigh data transmission for modern network communication is more and more urgent.Multiplexer (MUX) and demultiplexer (DEMUX) can be used to increase the data transmission rate. Multiplexer integrates several low-speed data streams into one high bit rate data stream on the transmitter side, and on the receiver side the data stream after regeneration is split up into original low bit rate channels by the demultiplexer. Most ultrahigh speed demultiplexers adopt GaAs,Si Bipolar,BiCMOS proesses, tree-type structure and SCFL logic. With the advancement of micro- electronics ,10Gbps and above bit rate demultiplexers can be implemented in 0.18μm or more advanced process. As for 2.5Gbps demux, 0.25μm CMOS process can satisfy the design requirements very well and the demux structure can adopt single serial-type, parallel-type, tree-type or the combination of the above three types , furthermore, the SCFL logic, pseudo-static logic ,TSPC and other logics can be applied in the design. Thus the design of 2.5Gbps demux is very flexible and convenient in the tradeoff of power consumption, chip area, operation bit rate and so on.A comparison is drawn between the three main structures of the demux: serial-type, parallel-type and tree-type. It also introduces the key circuits and the design consideration of the demux such as frequency divider, buffer, single-end signal to differential signal circuit, input and output I/O, etc. For most demux ICs consume large power because of using SCFL logic, we propose a low power consumption and giga-bit rate 1:16 demux with CML I/O interface by using the CMOS pseudo-static logic in 0.25μm CMOS technology. The chip area is only 1.56×1.86 mm2. We analyze the CMOS pseudo-static logic in detail and optimize the parameters to increase its speed . Thus the pseudo-static logic with the optimized parameters can meets the need of high speed and low power consumption. The on-wafer test results show that , with 2.5V power supply ,the 1:16 demux can operate correctly at 2.2 Gbps and the power consumption is 270mW; with 3.3V power supply,it can operate correctly at 2.5Gbps and the power consumption is 540mW. The result indicate that using the pseudo-static logic with optimized parameters and tree-type structure, a 1:16 demux consumes very low power and can operate in giga-bit rate.So this design not only makes grate sense for the research on low power consumption demux,but also provide a active referece on the development of other high speed and low power consumption digital ICs.