The Design And Implementation Of A High Performance 3D SRAM

3D SRAM(three dimensional integrated structure of SRAM) is an effective breakthrough for the bottleneck of performance, power consumption and area of traditional SRAM; With TSV to short the long interconnection of critical paths can boost the performance of SRAM chip; By dividing and stacking the memory array to minimize the length of the global interconnect in order to reduce the power consumption of memory arrays; Using the stacked Die to cut down the chip area. Aimed at a high-performance 128 Kb 3D SRAM, this paper established the structure and design specification based on the strategy of sub-array partition, and completed the function verification of the structure and the performance evaluation. In this paper, the innovation and the main work are as follows:1.In order to measure the relationship between the critical path to be shorten and TSV overhead in 3D SRAM, the method of linear programming was adopted to quantify the decreased degree of equivalent capacitance, which can give 3D SRAM designers an appropriate TSV using strategy. Then, the 3D SRAM partitioning strategy can be determined through measuring the three kinds of latency profit based on it.2.For the general analysis of the latency advantage of sub-array partition strategy,this paper modeled the critical path of memory array based on the sub-array partition strategy. Through comparing it with delay model of conventional structure, the paper proved that sub-array partition granularity can reduce above 40% delay.3.In order to take advantage of the structure of 3D SRAM, this paper proposed an optimized 3D SRAM structure; With TSV replacing the long interconnect to weigh the performance benefits from different partitioning strategies, and then determined the suitable partitioning strategy in the 3D SRAM. This paper established the reasonable design specification for 128 Kb SRAM, and divided the whole memory array into 16sub-array, and the size of each sub-array is 512 x16 bit.4.For the main circuit module, the delay analysis and functional verification are completed; the big drive problem of sharing TSV in memory array got optimized, the affect delay was cut down to 14 ~ 30 ps.5.Verifying the system function of the 3D SRAM, and simulating the 3D SRAM and traditional SRAM were based on 40 nm technology. The analysis showed that there were obvious advantages in dynamic power consumption and delay of critical path,among which dynamic power consumption reduced by 22.2% and the access latency of critical path decreased by 19.6%.