A Mobility Model Caused By TSV-Induced Stress And Its Application Research In The SRAM Performance Analysis

In recent years, the three-dimensional integrated circuits(3D ICs) based on the TSV technology has gradually evolved into one of the main directions of the development of microelectronic integrated circuit technology. As a vertical interconnect technology in 3D ICs, TSV technology can reduce the length of interconnects, decrease the chip area, improve the chip performance, and realize the integration of heterogeneous. Due to the difference of the thermal expansion coefficients(CTEs) of interconnect material and silicon substrate material, the TSV technology can induce the thermo mechanical stress, which can change the silicon substrate carrier mobility. Furthermore, the variantion of the mobility can affect the characteristics of devices and e the performance of the chip circuits.The paper firstly puts forward stress distribution induced by the TSV matrix and mobility variance analytical model. Secondly, how the stress induced by TSV matrix affect the current characteristics of MOS devices and timing characteristics of Inverter is analyzed based on the model. And then the arrangements of MOS transistors are optimized according to the keep-out-zone(KOZ) induced by stress. At last, the influence of the stress induced by TSV matrix on static random access memory(SRAM) circuit unit's performance is studied, and base on which the arrangement of each unit in the SRAM is optimized. The main results of the paper are summarized as follows:1. Based on the single TSV induced stress distribution and mobility variance analytical model caused by the stress, TSV matrixs induced stress distribution and mobility variance analytical model has been developed by the principle of linear superposition. And then a discussion of the effect of distance between TSVs, hole diameter,crystal orientation, carrier concentration, process temperature, and via materials on mobility variance is made.2 The effect of the stress induced by TSV matrix on the performance of the device is studied. An analysis of the impact of stress on the current characteristics of MOS transistors and the timing characteristics of the CMOS inverter has been made based on the TSV matrix mobility variance models with simulation. And based on which the arrangement of each unit in the SRAM is optimized.3 The application of the TSV matrix induced stress to the SRAM circuit unit is studied. Based on mobility variance models caused by induced stress, a research of the effect of TSV matrix induced stress on the performance of SRAM circuit unit is made combining with HSPISE simulation. According to the influence of the stress induced by TSV matrix on the static noise margin(SNM) of SRAM circuit, the arrangement of each unit of the SRAM circuit has been optimized to realize the improvement of the circuit performance.