Embedded SRAM Performance Model And Optimization

With the improvement of semiconductor manufacturing process and IC design capability, various types of circuits have already integrated into one chip which is called SoC (system-on-chip). With the increasing demand for large data throughput and the requirement of lower system power consumption, the embedded memory demand is increasing rapidly. It is forecast that memories of different functions will have occupied approximately 90% chip area by 2010. Thus embedded memory will become the determining factor of the whole system. Embedded SRAM is the indispensable component of embedded memory due to its low power consumption and high speed. It has played a positive role in improving performance and reliability, lowering cost and power consumption.The embedded SRAM performance model, structure optimization and memory cell device dimension optimization are studied in this article. Firstly, in view of the hierarchical embedded SRAM structure, this article establishes SRAM macro block performance statistical model and control logic circuit delay analytical model. Combining these two performance models, an embedded SRAM performance hybrid model is proposed. The boundary of analytical model and statistical model is clearly divided in this performance model, and evaluation accuracy is improved. Secondly, based on embedded SRAM performance hybrid model, this article adopts bionics algorithm-ant algorithm to optimize hierarchical embedded SRAM structure. This method which adjusts memory system structure improves memory system performance. Finally, considering the factors such as memory cell area, power, delay and reliability, this article establishes static 6-T memory cell area, power, delay and static noise margin equations, analyzes 6-T memory cell device dimension constraints under "read upset" and "write upset", then proposes a method to enhance embedded SRAM performance by optimizing 6-T memory cell size.In order to realize embedded SRAM design and verify proposed optimization methods, this article takes the Garfield202 system chip as the platform, which embeds A720T processor and 20KB Scratch-Pad memory(SPM). A720T processor takes ARM7TDMI as processor core, integrating 8KB Cache. First of all, this article adopts SRAM compiler and full custom design method to design SPM and Cache. The chip test results show that on-chip memory function operates correctly and instruction executes faster. Secondly, the embedded SRAM structure optimization method is used to optimize SPM performance. The experimental simulation results indicate that SPM reduces 25% dynamic power, but merely increases 8% area and 2% delay (system requires power preference). Finally, SRAM memory cell dimension optimization method is used to optimize the SRAM memory cell of cache. The experimental simulation results indicate the A720T reduces 12% chip area and 10% power consumption.