Rearch On Key Techniques Of Super High Speed Digital CMOS Image Sensor

With the rapid development of the semiconductor fabrication and circuit technique, some key defects of CIS, such as dark current, noise, fill factor and dynamic range, have been surmounted. CIS is widely applied to consumption digital product, medicine and industry surveillance, with the superiority in low cost, low power consumption, easily integrating and reading flexibly. CIS is gradually replacing the dominant station of CCD image sensor. Going with the expanding of the pixel array,"high speed"becomes the new trend of the CIS.For meeting the CIS requirements of large data throughput and high image quality, by analyzing and comparing three types of digital CIS, the column parallel system is chosen because of its high speed, high image quality and facility to expanding pixel array. Two high speed column parallel digital CIS processing systems are proposed for different high speed application, which have the high frame rate of 30~1400 Frame/s for VGA level CIS. The first low dissipation and high speed system adopts a single slope ADC and the second one integrates PLL, RSD cyclic ADC and LVDS circuit in it. The structure and working principle of the two systems are expatiated. The critical modules and a swatch of the system with single slope ADC are taped in 0.35μm process. The swatch can capture clear dynamic image, and the critical modules'testing data are according with the design target, which prove the correctness of the system design.The creative works of this paper include: a technique that the sample capacitor and the load one are converted every cycle is proposed for cyclic ADC. Based on the charge transfer of switch capacitor amplifier and cyclic operation of cyclic ADC, this technique makes the amplifying simultaneously with the sampling. Cooperating with capacitor splitting technique, it leads to triplicate speed of the primary one without hardware increase.A reverse offset storage technique is proposed for cancelling the CIS column FPN. In the sampling phase, the feedback capacitors are connected crosswise between the input and output of the amplifier, to make the offset voltage not to be accumulated to the output. Cooperating with double sampling technique, it reduces the column FPN which is due to pixel and processing circuit, to a value within the tolerant deviation.A tipical reset technique for five transistors active pixel is proposed. Based on the accordant deviation of threshold voltage of adjacent transistors, hard reset is emploied before soft reset to reduce the FPN, which is induced by transfer transistor of pixel and can not be eliminated by double sampling technique. No extra process is needed in this technique, so the cost is low.