| Modern electronic systems have stepped into an era of complicated System -on-a-chip (SOC), but the mature of digital processing technology makes analog-to-digital (A/D) converter as a neck of performance improvement of the whole system. To satisfy the request of low power dissipation of high-resolution and high-speed A/D converters in portable applications such as high-resolution imaging and wireless communication, this paper is to design low power dissipaton subcircuits for a 30Msample/s, 14bit pipelined A/D converter.In this paper, I do first to compare the performance characteristics of various types of A/D structures, and adopt pipelined architecture for our converter design due to its good tradeoff between high speed,high resolution and low power dissipation. Then, I analyze its operational principles and characteristics, and choose an optimum 1.5bit resolution per stage. Following that, non-idealities affecting the performance of ADC are analyzed in detail, and several kinds of technologies are introduced to eliminate or reduce all the non-idealities, and bottom-plate sampling and digital calibration technology are emphasized. Finally, subcircuits for implementing pipelined ADC are designed on the 0.6μm CMOS device model with theoretical analysis, and the main subcircuits' layout is realized in full custom design method.The simulation results show that the subcircuits meet with our design request. The innovations in our design are that: 1,the whole A/D converter is designed on the method of top-down design; 2,a gain boosting telescopic cascode operational amplifier is chosen to improve the gain and bandwidth, but the system power dissipation is reduced and the power dissipation of the main part of amplifier is only 2.6mW; 3,the most critical comparator in sub-ADC is chosen as a dynamic comparator for reducing the power dissipation greatly, which is robust to technology variation and device mismatch, and its power dissipation is only 155μW. |
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