Font Size: a A A

A12-bit100MSPS Reconfigurable Pipeline A/D Converter

Posted on:2014-11-30Degree:MasterType:Thesis
Country:ChinaCandidate:Y F ZhangFull Text:PDF
GTID:2268330401453812Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of wireless communication technology, wireless application environment is moving to faster transfer rates, higher transmission quality and multi-standard communication protocols. High-speed A/D converter is the most critical component of the multi-standard wireless terminal device and has large impact on the overall function of the communication system, so its research has long been the hot and difficult research content in both China and abroad.This thesis describes a low-power configurable pipelined A/D converter suitable for multi-standard wireless applications environment. The front-end of the A/D converter is removed without sample-and-hold circuit (SHA-less structure), together with the dynamic latched comparator in sub-A/D converter, which greatly reduce the power consumption and area of the A/D converter. To meet the error requirement of the SHA-less structure and the dynamic latched comparator, classic1.5bit-stage structure is applied. Finally, for the use of multi-standard wireless application environment, the A/D converter has three configurable design, including the function of adaptive power consumption proportional to frequency, SPI programmable op-amp and the eight operating mode.Based on SMIC0.18μm1.8V1P6M CMOS process, the overall simulation results show that for10-bit resolution, A/D converter’s SNR is57.31dB, SFDR is60.59dB, ENOB is8.95Bits, for12resolution, SNR is61.31dB, SFDR is58.63dB, ENOB is9.45Bits, which readily meet the performance requirements of the high and low resolution mode; the first level MDAC simulation shows that:with the tuning of SPI programmable op amp, dynamic performance parameter (SNDR) of single-stage MDAC raises approximately lOdB; the simulation of frequency adaptive function shows that the adaptive range of the A/D converter can be configured from10M to100M, while the performance parameters remain virtually unchanged, the A/D converter’s power consumption is14mW to135mW, achieving the aim of the power consumption proportional to frequency.
Keywords/Search Tags:Pipeline A/D Converter, Resolution Reconfigurable, Power ScalableSHA-less, CMOS
PDF Full Text Request
Related items