The Design And Implementation Of A Multiple Modes Turbo Decoder IP Core

Since the birth of Turbo codes, it has received widespread concern and in-depth study in the field of communications because of the excellent performance closing to the Shannon limit. With deeper advancement of the long-term evolution and the arrival of 4G era, we put forward higher requirements for reliability and validity of information transmission. Turbo codes has been the hot study as one of the wireless channel coding standard. In this paper, we design a multiple modes Turbo decoder IP core aimed at increasing the throughout and decoding efficiency based on in-depth theory study.Using top-down design methodology, this text completes the design and verification of Turbo decoder IP core and then carries on the performance analysis. The main contents of this paper include:1. Completing the performance simulation of Lookup-Log-MAP algorithm based on the MATLAB platform, ultimately determining the algorithm to be the decoding algorithm used in the design.2. Roundly design and implement a multiple modes Turbo decoder IP core which supports 3G communication protocol. The IP core uses standardized interface, include data interface design based on the AXI bus protocol with greater bandwidth and flexibility, and configuration interface design based on the APB bus protocol with higher stability and effectiveness.3. To improve the coding efficiency and reduce delays, the IP core uses parallel decoding structure within four SISO modules. Each SISO decoder module uses an improved sliding window algorithm, improves the efficiency, supports any case of number range to be configured, improves the scalability of the device. Using two single-port memories to store the alpha metric values within “ping-pong” operation, reduces the complexity of control logic and hardware implementation, the memory capacity is reduced 3/5 compared to without sliding window. Designing the stop decoding criteria based on the statistical properties of the extrinsic information, effectively reduce the decoding delay without reducing the decoding performance.4. The IP core increases the buffer module between the memory unit and the decoding unit, designed to solve the problem of data lack from the memory unit to the decoding unit, prevent the occurrence of access conflicts.5. With overall verification, the IP core’s functions are right. The actual working frequency reaches 400 MHz based on 65 nm CMOS technology. The BER and decoding rate reach the requirements of multiple modes Turbo decoder IP core.