Efficient Ctc Decoder In The Fpga-based Design And Realization

Convolutional turbo code is the channel coding scheme which concatenates two simple convolutional codes in parallel. By employing a suboptimal iterative decoding structure with SISO maximum APP decoding algorithm, a better performance is achievable at a feasible decoding complexity. A noticeable feature of CTC is introducing interleaver in the coding and decoding structure, which effectively reduce the correlation of code word, the simulating result in AWGN channel shows, the near-capacity performance is achievable by CTC.Compared the computing complexity and performance of popular CTC algorithms for decoding with computer simulation, we choose enhanced Max-Log-MAP decoding algorithms with low complexity and good performance in this design, we could see that the better decoding performance is acquired.On the basis of introducing BCJR algorithm, symbol-by-symbol MAP algorithm , Log-MAP algorithm , Max-Log-MAP algorithm and non-binary symbol-by-symbol enhanced Max-Log-MAP decoding algorithm are discussed here, and SOVA as a implementing scheme is also proposed here, the complexity and performance of those algorithms are discussed.Analyzing the performance of CTC decoder based on the platform of C language, discussing several key parameters of designing CTC decoder. Proposing some basic rules to design optimum schemes of CTC decoderAs CTC decoder is designed, the techniques of interleaver and slid window are used in this design. At last, the RTL model of decoder is described with Verilog HDL.The model is simulated on the Active-HDL platform, the result based on compared with C language model shows the RTL model has similar performance as C language model. FPGA verification scheme for CTC decoder is designed, and performance testing is fulfilled in the baseband systerm of WiMAX. These studies of this thesis provide the foundation of designing CTC decoder with better performance in the wireless baseband system in future, so they are very important.