6 Bit Super Speed Flash ADC Design

Analog-to-digital (ADC) converter is the key device of advanced communication rada acoustic susceptance and many consume eletronics .As a special interface connects with analog and digital circuits, high performance analog-to-digital converter is more and more important in whole system design. Now the development of the technology has more need of the performance of the ADC , especially the speed. It even has become the key factor of the device performance.This paper chooses Flash ADC as a object to study after analysis some high speed and resolution ADC structure nowadays. Beginning with the principle of the Flash ADC the thesis analysis its function and characteristics, then parts system into some sub-modules to further research. Because of the necessity of the high-speed ADC offset , bandwidth of the op-amp that is vital for the system design, optimization for different building blocks and digital error correction are used in this paper. The simulation indicated that it can achieves 5.9 bits for input frequency up to 16.6 MHz at 1Gsample/s. The maximum sampling speed is 1GHz. Simulated peak INL and DNL are less than 0.4LSB and 0.2LSB, respectively. This ADC consumes about 400 mW at 1Gsample/s.The chip fabricated in 0.18-μm CMOS process technology 1.8v supply.