Analysis Of Static Mismatch Error For High-Speed High-Accuracy Digital To Analog Converter

The speed of contemporary digital circuits has grown rapidly.Data converters(ADCs/DACs),which connect digital and analog signals,have had higher requirements on their speed and performance,and have become a research hotspot.Moreover,data converters are widely used in many fields such as wireless communications and high-definition video,and are important modules that affect system performance.In this paper,the effect of the static mismatch error of the current source on the static performance and dynamic performance of the DAC is studied.A 10-bit 10 GSPS D/A converter is designed using SMIC 40 nm process to investigate the known current source array layout scheme.Optimize the layout of the current source array by simulation,in addition to the learning and application of dynamic element calibration(DEM),use DEM technology to eliminate the correlation between the output error and the input digital code,in order to use DEM to optimize the DAC The results of the output,and finally described in other static mismatch error reduction or elimination of the calibration method,such as self-calibration,random clock full calibration.At the end of the article,the design of the indispensable circuit in the DAC implementation is introduced,such as the decoding circuit,unit current source circuit,and the switch driving circuit.This thesis firstly introduces the working principle of DAC,selects current rudder type DAC which is more widely used,and then takes the premise of determining the static mismatch error model,and studies the effects of segmentation on DAC performance,and then implements 10-bit DAC.Subsection,based on MATLAB modeling,simulation and analysis and comprehensive consideration of the DAC's INL,DNL,glitches and area and other key factors,the final choice of 4+3+3segmentation,segmentation decoding The method is different;the focus of this paper is to study the impact of static mismatch error on the DAC main index,which is divided into systematic error and random error,which have different effects on the performance of the DAC;in order to better understand the static mismatch error The source of this article is to study the design method of the current source,conduct thesimulation of transistor-level current source circuit structure in Cadence,get the desired current source output current,design high cross point switch drive circuit;It simulates the “4+3+3” segmented DAC under different current source array arrangement,different system errors and random error settings.Obtained DNL,INL,SFDR and ENOB and other characteristic parameters,in order to analyze and find the optimal current source arrangement structure;Because the current source layout is determined,the fixed digital code input fixes the output,and also has a fixed error,which makes The error is related to the input.This paper studies the DEM technique to optimize the performance of the DAC.In addition,it also briefly introduces the elimination or reduction of the static mismatch error by other calibration methods.Finally,the design of other circuit modules that constitute the DAC is briefly introduced.To complete the implementation of the 10-bit DAC.Finally,an optimized current source array layout is achieved,and DEM randomization is implemented.The DAC optimized for these two aspects is simulated,and the results obtained can achieve the desired effect and have the effect of optimizing the performance.