The Study Of The Folding And Interpolation Analog To Digital Converters

With the development of mobile multimedia, especially the development of vedio, the high speed, low supply, small area ADCs are becoming more and more important. Recently, since BJT's high quality and performance, people usually used the bipolar (BJT or BICMOS) technology to realize the high conversion ADCs design. However, it is difficult to use the same masks of the bipolar technology in realizing digital signal process. At the same time, the bipolar technology will consume more power dissipation in contrast with the CMOS technology. Therefore, in the modern SoC design, the CMOS technology is easier to realize the design.Based on the comparison of the different arithmetic of the high conversion rate analog to digital converter (ADC), a folding and interpolating architecture ADC was deeply analyzed. On the other hand, we further analyzed the constraint factors about how to improve the performance of the folding and interpolating architecture analog to digital converter design. Contrast with the traditional full flash architecture ADCs, the Folding and interpolating architecture ADCs require least comparators and decrease the power dissipation of the system. It can also provide high conversion rate and medium resolution. So, this architecture is very fit to the application of SOC.In this design, two paralleled ADCs, one is a fine 5 bits quantization with folding and two level cascade resistor interpolating architecture and the other is coarse 3 bits quantization, were suggested to realizing the 8 bits resolution. This...