Research On Technology Of Establishing Radiation Harden Standard Cell Library Based On 0.13?m Process

In recent years,integrated circuits have developed rapidly in various fields,and the requirements for chip performance and reliability have gradually increased,especially in the aerospace field.Due to the complexity of use scenarios,aerospace chips have strict requirements for reliability.At present,the standard cell libraries provided by process manufacturers usually have basic logic functions,and the circuit structure used is also the most classic and commonly used structure,which cannot meet the reliability requirements of aerospace chips.Therefore,based on 0.13?m commercial process,the establishment process of the radiation harden standard cell library is explored.The circuit design and layout design of standard cells need to follow specific design principles and follow corresponding design principles.This article explains the determination of transistor size and the optimization of complex gate units when designing unit circuits.In the layout design,it is specified that the cell height needs to be same;in order to avoid the effect of metal electromigration,the width of the power / ground line also needs to be designed according to the parameters provided by the process manufacturer;the position of the PIN in the layout determines The complexity of the floorplan and routing work.The PIN need to be placed in a reasonable position;in order to make the layout denser and the area utilization rate higher,the floorplan algorithm of the transistors in the layout is also explained in detail.This article compares common redundant radiation harden ideas,and proposes a new combination logic cell radiation harden method,and simulates the single-particle effect on the Cadence platform using a dual exponential current source model.In the design of the standard cells,the radiation harden method of the D flip_flop was emphasized.The radiation harden strategy is used to prevent double-node flipping.The setup time and single-particle effect simulation were carried out on the Cadence platform.At the same time,it was compared with ordinary D flip-flops in terms of transistor number,layout area and settling time.This paper uses the Encounter Library Characterizer tool for characterization,and uses Abstract to extract abstract view.Apart from the characterization process of standard cells,the content and format of the extracted files are introduced in detail.At the same time,the extracted files are integrated to form the final library timing file(.lib)and abstract view file(.lef)of the standard cell library.In order to ensure that the radiation harden library in this paper can be used by mainstream EDA tools,a four-bit counter and a 3-8 decoder are used as simple examples.The Design Compiler is used for logic synthesis,and the INNOVUS tool is used for layout.Therefore,it has been preliminarily proved that the radiation harden standard cell library can be identified and called by mainstream EDA tools.