Ultra-deep Sub-micron Standard Cell Library Design For Manufacturing Technology Research,

As VDSM(Very Deep Sub-micron) era has come in IC design, Sub-wavelength Lithography is widely used in semiconductor manufacture process. That makes the printed shapes on silicon wafer are not the same as mask patterns. The distortion in pattern transferring process may influence functionality and performance of IC products and lower the production yield. Resolution Enhancement Technologies are new used in Sub-Wavelength Lithography circumstance to partially solve the incurring manufacturability problem. However, with the Sub-Wavelength Lithography continues extending to its physical limit, new kinds of problems of IC manufacturability and yield keep emerging. This is one of the most concerned research issues for global IC industry and academia now.This dissertation tries to investigate some kinds of problems of IC manufacturability and yield by studying physical design rules. He flow of IC design and manufacture is described. All three types of yield loss, which are serious impacting yield outcome in today's nanometer IC designs, and the problem of manufacturability on physical design rules are analyzed. We build a framework to evaluate recommended design rules based on edge-placement errors or CD tolerence and are of test circuits. Based on this framework, some recommended design rules which are fit on the beginning of low yield process of low yield process in nanometer process are summarized.