Research And Development On Embedded Image Processing System

Presently, image processing system is applied to the fields that include industrial production, military and medicine widely. The mainstream image processing system, which is constituted by CCD camera, image acquisition car and computer, has some disadvantage of complicated structure, high-cost, large cubage and so on. In recent years, with the incessant development of sensor, semiconductor and embedded system technology, a new image processing system, namely, embedded image processing system stepped into course of development mileage of image processing system phylogeny. Wherewith the advantage of high-performance processing ability, reliability, small cubage, low power, low cost and good-security, embedded image processing system, which has extensive prospects, can conquer the disadvantage of conventional image processing system effectually.Based on the conception of integrating embedded system and image acquisition & processing, this dissertation researched and developed an embedded image processing system that was composed of image acquisition system, front signal acquisition system and digital image processing system. In the hardware design, through the function analysis of each sub-system, the kernel-processing devices of the sub-system were confirmed and the main principle block diagram of the system was provided. Ulteriorly, the electronic circuit of the power function module, CCD driver function module, image acquisition function module and image processing function module were designed, and then the interfaces of each module were also designed. Theory analysis and experimental result indicated that electronic circuit worked normally, working signals conformed to the project requirement and the CCD analog signals were accurate.In the software design, though the analysis of the function requirement and the mutual relationship of each module, the timing of each module were designed and the state machine diagram was given based on the control kernel CPLD. By dint of the tool MAX+Plus II, the state machine design was emulated. The experimental result indicated that the actual output timing was the same as the timing of theoretic design. Based on the 32bit embedded MPU ARM being the image-processing kernel, the ARM bootloader was design and the flow chart of data acquisition was given.