Low Power Design For Viterbi Decoder

Convolutinal coding is a coding scheme often employed in digital wireless communications.Viterbi decoders are used to decode convolutional codes.Viterbi decoders employed in digital wireless communications are complex and dissipate large power. With the proliferation of battery powered devices such as cellular phones and laptop computers, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of Viterbi decoders for wireless communications applications.In CMOS technology the major source of power dissipation is attributed to dynamic power dissipation, which is due to the switching of signal values. The focus of our research in the low-power design of Viterbi decoders is reduction of dynamic power dissipation at logic level in the standard cell design environment.The VD is composed of four functional units:1) The branch metrics unit (BMU);2) The add-compare-select unit (ACS);3) The path metrics unit ( PMU);4) The survivor memory unit (SMU);Regarding the power dissipation of the Viterbi decoder, the SMU is the hottest spot in the Viterbi decoder due to the frequent memory accesses.There are two traditional techniques for the realization of survivor memory unit in viterbi decoder--register exchange (RE) and trace back (TB) method. RE has a very complicated interconnections and needs a high power consumption .TB needs a large quantity of buffers and has long decoding delay. In this paper a modified register-exchange (RE) method is presented, which reduce its memory access rate and its amount of memory, thus, reduces the power consumption. Based on the modified register-exchange (RE) method SMU, a Low power viterbi decoder can be designed. Our experimental result shows the proposed design reduces the dynamic power dissipation of a Viterbi decoder by about 33 percent compared with the one without considering the low-power design.