Research And Design Of High Performance Multimode Viterbi Decoder

The Viterbi algorithm is an optimal sequence decoding algorithm based on trellis graphs.This algorithm is widely used in various communication systems with its excellent error correction performance.However,with the development of communication technology,a variety of communication standards have emerged.When these standards perform channel coding error correction,most of them use a combination of convolutional code and Viterbi algorithm.Each standard has a different encoding form,and each form puts forward different requirements for the decoder.In addition,manufacturers have a strong interest in building communication devices or systems that can operate under multiple standards.This means that communication devices must not only be compatible with these communication standards,but also have the ability to dynamically switch these standards.In order to meet the various communication standards existing in the communication system,a high-performance multi-mode Viterbi decoder is designed and implemented in this paper.This paper deeply understands the decoding algorithm and principle of convolutional code,and according to the design requirements,the Viterbi decoder has been designed,verified and synthesized logically.The research mainly focuses on the following aspects:Study the basic principles of Viterbi decoding,discuss the decoding method that supports multi-rate and multi-constraint length based on the Viterbi decoding theory.According to the requirements,it is designed to support both soft and hard decision modes.At the same time,the constraint length can be 5-9.Single shift register convolutional codes with coding rates of 1/2,1/3,and 1/4 are operated.The code rate and constraint length are determined by polynomials,and any frame length is supported.Analyze the latest research methods of each module in the Viterbi decoder,determine the overall design plan,and complete the decoder design.Among them,the ACS calculation unit adopts 4 ACS cascade structures with a base of 16,which performs 4 ACS operations in each cycle and runs on a sub-grid graph with a base of 16,thus skipping the four grid stages The three-stage state measurement memory input and output operation of the state measurement memory,thereby reducing the bandwidth of the state measurement memory by 75%;The survival path management part adopts the combination of backtracking method and sliding window,and supports three backtracking methods.This management method can solve the problem that the survival path memory cannot store large amounts of data during decoding;In order to solve the problem of metric overflow,an improved modular normalization method is proposed.Compared with other designs,the path metric calculation result in this design adopts 13-bit signed quantification;At the same time,in order to determine whether the decoding result is reliable,there is a 1 bit Yamamoto judgment bit after each "additional selection" calculation.In order to ensure the correctness and completeness of the design,after the design is completed,the various modules of the Viterbi decoder are verified according to the design requirements and the working mode of the decoder,and system-level verification is performed at the same time.Using MATLAB software to analyze the bit error rate of the decoder in different modes,the results show that the decoder fully meets the requirements of multi-functional design,is suitable for multiple communication standards,and obtains good BER performance.According to the requirements of the project,55 nm CMOS process is adopted,According to the requirements of the project,55 nm CMOS process is adopted,and the working frequency reaches 350 MHz after synthesis.