Researches And Implemention On Viterbi Decoding Algorithm

Based on the analysis of the previous research work, we proposed one way to fully realize the Viterbi decoder with the method of register exchange and we made some improvements in details. At first, with the help of the software Matlab 7.0, we built a complete testament system, including coding & decoding, modulating & de-modulating, and the process of transmission in channel with noise. Furthermore, by software simulation we also did some comparisons and analysis on soft-decision bits, delay depth and computing methods on metrics. We then realized it in Verilog HDL, identified the main architecture of the decoder, and balanced the contradiction between the synthesis area and bit error rate. Some parameters, such as soft-decision bits and the delay depth are adjustable before compiling. A series of methods to further enhance the Viterbi decoding performance are adopted, such as path-cutted, equivalent startup process and parallelized ACS computing. We simulated it with ModelSim 6.0. In this procedure, since tens of thousands of decoded data will be exported into text files, it is impossible to compare and know if the data were right. Therefore, we made a more intuitionistic program with MFC. With the software Xilinx ISE9.1i, we then synthesized the code on Virtex 5 environment, the equipment named XC5VLX330. Results show that the maximal frequency of the output data speed is close to 200Mbps. Then we downloaded it into HAPS-54 board, and made the BER tests in the actual system. It comes to the conclusion that the IPCore of our own surpasses that of Altera and CMD-600, when the SNR is higher than 5.0.To be more practical, following the DVB-S System, we cascaded the convolution code as inner code with RS code. At the same time, we adopted the block-interweaving technology in our design and ascertained the interweaving Matrix and design blue print. On these improvements, the ability of decoding and anti-bursting-error ability was further enhanced.