Research On Algorithm And VLSI Design For Digital Signal Processing Of 1000BASE-T Transceiver

IEEE802.3ab 1000BASE-T gigabit Ethernet (GbE), a successor to IEEE802.3u fast Ethernet(FE), is a new generation of high speed Ethernet standard based on twisted-pair channel. The main purpose of 1000BASE-T is to achieve 10 times the transmission rate as that of the fast Ethernet on the same Category-5 unshielded balanced twisted-pair utilized in 100BASE-TX fast Ethernet, while the bit-error rate is not more than 10-10. Through the application and network management available now and the full compatibility of user resources including the cabling system, 1000BASE-T can be upgraded seamlessly from fast Ethernet while the upgrade cost is cut down to minimum and good features such as simple and cheap structure, high reliability and easy management are inherited. 1000BASE-T GbE is gradually becoming the mainstream Ethernet standard due to its notable advantages of high bandwidth and low cost. It can be predicted that 1000BASE-T GbE will have broad application and market prospects.However, the tremendous technical challenge in the transceiver design is a stark contrast to the great advantages in application. As 1000BASE-T GbE transmission medium is used in the design of the previous generation of Ethernet standards, four pairs of UTP for full-duplex transmissions and multi-level modulation technique for bandwidth efficiency improvement are employed in 1000BASE-T in order to provide 10 times the transmission rate. But full-duplex bi-directional transmissions pose a serious echo and cross-talk problems. Hybrid circuits and echo cancellation technology are used to eliminate the interference between bi-directional transmissions. To make compensation for the SNR loss caused by the multi-level modulation technique, a much more complex coding algorithm is realized compared to the one in 100BASE-TX. Higher throughput and more complex algorithms bring a lot of difficulties to the design of the transceiver. The baseband signal processing module in the physical layer, in particular the joint TCM decoder and equalizer is one of the main difficulties.To fully meet the specification of the transceiver, the major issues are how to eliminate the non-ideal characteristics in the actual UTP channel and how to take full advantage of the coding gain of the algorithms in 1000BASE-T. A few commonly used decoding algorithms have been proven to be unable to do the job and the tremendous hardware overhead comes together with the high performance algorithm, or has been considered too difficult to achieve the required throughput. In the mean time, the decoding algorithm is expected to be implemented with low hardware complexity to reduce the transceiver cost as well as with low power consumption in the application of mobile equipment. We believe that there is still much room for improvement of the existing research in these areas. In view of this, we present in this paper an in-depth study on the design of high performance, low complexity and low power consumption decoder in the actual 1000BASE-T channel environment, and propose effective solutions.The following is the main research aspects of the paper:(1) To deal with the problem of damaged 4D symbols caused by delays, exchange or wrong polarity between twisted-pairs, we deeply studied the coding technology used in 1000BASE-T, exploited the coding characteristics and propose PCS training methods with the premise of possible error polarity or order in twisted-pairs. Thus paving the way for the completion of decoding.(2) To determine the best joint equalizer and decoding algorithm for 1000BASE-T, we analyzed several joint equalizer and decoding algorithms that meet the demand of 1000BASE-T high-throughput application on the basis of elaborate research. We simulated those algorithms to verify their performance in the 1000BASE-T channel environment. The key parameters are taken into consideration and their impact on complexity and performance is compared. Pre-filtered M-Algorithm is proposed, which reduces greatly the complexity of hardware and performs much better than commonly used PDFD.(3) To solve the high critical path latency problem of MA decoder, we propose a MA4 decoder with look-ahead technology. Optimal look-ahead structure, low fan-out decoder structure and low complexity sorting network optimized for M-Algorithm are employed to reduce the critical path delay to almost the same as that of PDFD while maintaining the advantages of low complexity. Symbol compression technique further reduces the M-Algorithm decoder hardware complexity. By these means, the 14-tap MA4 decoder still has the performance advantages over 14-tap PDFD under 1 Gbps throughput. Meanwhile, the hardware complexity is two-thirds below compared to that of the latter. (4) To further reduce the pre-filter PDFD hardware complexity and power consumption, a hybrid structure SMU is proposed and analyzed in different constraints such as area, power and decoding delay. We prove that hybrid structure SMU has more area and power consumption advantages over the traditional register exchange architecture SMU. The application in 1tap pre-filtered PDFD indicates that the utilization of the hybrid structure SMU can reduce 19 percent of hardware complexity and half the power consumption.(5) To select felicitous joint TCM decoder and equalizer in different design constraints, the pre-filtered joint equalizer and decoder applicable to various sizes and performance conditions is analyzed on the basis of the existing and proposed techniques. The structures adjusted to low or high complexity constraints are proposed. Through simulation and physical design, we make sure they are suitable for 1000BASE-T transceiver and have integrated hardware complexity or performance advantages over existing ones.(6) To increase efficiency of joint TCM decoder and equalizer when IDLE symbol is transmitting in 1000BASE-T Ethernet, we make use of 1000BASE-T coding properties and propose a dual-mode technique which can be applied to all types of pre-filtered joint equalizer and decoder. Simulation and physical design show that the power consumption is reduced to one-third below when network is idle with no loss of performance and a small increase in the complexity of hardware.