High-speed, Low-power Viterbi Decoder Algorithm And Circuit Implementation

With the development of wireless communication technology and emergence of various wireless application standards, the demand for fast, low-cost and low-power wireless communication systems is ever increasing. As a vital part in the wireless systems, error-correction code plays a key role in improving the system's overall performance, such as speed, power and hardware complexity. Moreover, the unique characteristic of wireless channel poses stringent requirement on the performance of error-correction code. Convolutional codes (CC) and Viterbi algorithm (VA) together are very suitable for wireless fading channels due to their high coding-gain and moderate hardware overhead, and are widely used in contemporary wireless systems, such as WLAN, DVB, MB-OFDM UWB, etc. However, those high-speed wireless communication systems make the realization of Viterbi decoder (VD) a challenge since low complexity, low power, high coding-gain and high speed are required.This thesis discusses the optimization of algorithm and architecture of VD to break the speed bottleneck and achieve requirement posed by those wireless communication systems. MB-OFDM UWB systems are particularly discussed as an example. The thesis first introduces the basic concept of digital communication systems and channel codes, and then discusses principles of CC and VA. Several techniques used to realize high-speed VD are discussed in detail. As an example, the thesis applies those techniques to the MB-OFDM's VD and shows how to choose specific architecture and parameters. Finally, potential techniques which can be used to further improve the VD are discussed briefly.