Research On Low Power Memory Design And Implementation In ROM

As IC densities and operating speeds have continued to climb, proving Moore's law again and again, designers have focused significant effort on the design of low power systems. With memories accounting for the large share of power consumption in the microprocessor, especially in SoC (System on Chip), low-power memory design technologies have significant meaning to the development of IC design.In high performance microprocessors, access time, core area and power consumption are three key parameters of embedded memories. In practice, these three parameters trade with each other, which makes it difficult to reduce power dissipation without involving the speed and area of the memory.In this paper, low power memory design technologies were studied at first and a 64kb (4k× 16bit) ROM was carried out by custom design method and fabricated in 0.18μm CMOS process. The whole design flow including logic, layout, tape out and chip test design was completed. A new selective precharge structure with charge compensation circuit proposed in this paper was adopted, and the power dissipation was significantly reduced. In typical case, the access time is 1.35ns. The average and max power at 500MHz are 28.2mW and 84.6mW respectively. Compared with the ROM generated by the memory compiler in same process, the ROM with low power structure reduces average power consumption by more than 65%, the access time is about 30% smaller and area increment is less than 3%. Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed build in self test (BIST) for IP core chip tests.