Research And Full Custom Design Of High Performance Arithmetic And Logical Unit

ALU is one of the most important and usually used computing units in microprocessors, the speed and power dissipation of ALU have important effect on the performance of whole microprocessor. The ALU designed with the methodology of full custom can realize higher speed, lower power dissipation and smaller area, and it has great value in application and significant meaning in practice.This thesis emphasizes on full custom design methodology of high performance ALU. The proposed 64 bits high performance ALU is optimized at algorithm level, logic level, circuit level and layout level, and is implemented in 0.18μm CMOS process. Furthermore, the testing technique of the ALU is discussed. This thesis mainly contributes to the following aspect:1. A new notion called"Performance-vector"to quantificationally measure the performance of core adder is proposed. According to the theory of"Performance-vector", an optimized high speed parallel adder algorithm is proposed. The algorithm combines with the advantages of Parallel Prefix Adders and Carry Select Adders to achieve a good balance among speed, power dissipation and area.2. Using"Logical Effort"method to analyze the circuit's critical path, and choose the optimized size of transistors in theory by this method. Then, using STA technique simulates and analyzes the circuit to optimize transistors size further, and the circuit optimization arithmetic based on STA is gained. Results proved that the optimization strategy of combining theory and practice have better effect.3. In typical case, the delay of critical path is 1.38ns, power dissipation is 45.3mW, and layout area of the ALU is 0.05112mm2. The design achieves the goal of higher speed, lower power dissipation and smaller area.4. A novel BIST technique for the proposed ALU has been discussed in the thesis. It can achieve 100% fault coverage with few test patterns. In conclusion, the technique has better efficiency and lower cost.