The Research Of Test Generation Methods Based On Controlled Linear Shifter

With the Integrated Circuit (IC)manufacturing technology improvement and the increase in chip area, large scale integrated circuit testing requires more test data.As System-on-a-Chip(SoC) has become the mainstream mode of IC development, single-chip integration of different types of IP cores,test data will be huger.The huge scale of test vectors will bring a number of problems.First,the test equipment needs large storage capacity to store these vectors;Secondly,the need for more test channels;At the same time,in order to provide at-speed test,the frequency of test equipment also needs to raise very high.All of these problems,make the proportion of IC testing in IC production costs increase, it also causes the challenge which the testing faces to getting more and more serious.Therefore,it needs to find new test methods to solve the problem of excessive testing costs.A good method to address this problem is Design-for-Testability (DFT).The fundamental idea of DFT is to consider the test issue while designing, in order to make the ICs can be tested easily. Build-In Self-Test (BIST)is a kind of most important and widely used DFT technologies,as a DFT technology it has become the first choice to solve the problem of board-level test and SOC test.The key of BIST scheme lies in Test-Pattern Generator (TPG) design.This paper proposes an at-speed test vectors generation method which is based on controlled linear shifter.In this method,corresponding test vectors were generated for each fault points,using these bits which are directly stored in ROM to control the first bit of linear shifter,linear shift the initial vector to match another, dynamically generate the test set.Experimental results show that this method on reducing the total test time and memory overhead is quite remarkable.As the method proposed in this paper is a test-per-clock BIST testing. As a at-speed BIST,the test circuit chip may fail or burned because of the continuing heat. At the end of this paper,we have carried on the optimization to power consumption under this test method, through carries on the choice to the original test set, when applying test vector or capturing the test response,massive irrelevant vectors have shielded,thus has reduce the test power consumption greatly.