Design Of Low Power And High Performance Pulsed Flip-Flops

With process scaling, power consumption increases drastically in VLSI. Moreover, an increasing number of mobile applications have a low power consumption demand in order to extend battery life. These factors necessitate the development of power consumption reduction techniques while maintaining system performance. Thus, power reduction becomes a pivotal concerning in current CMOS circuit design.The major fraction of the total power in modern synchronous systems, such as microprocessors, is dissipated over the clock system. Latches and flip-flops are basic elements of clock system and they account for the speed and power dissipation of the clock system. They have a large impact on both cycle time and energy consumption in modern synchronous systems. In some sense, flip-flops and latches act as a benchmark to determine the system performance. These factors boost the development of low power and high performance flip-flops.Pulse-triggered flip-flops usually exhibit higher operation speed than the master-slave flip-flops due to their soft edge and negative setup time. Pulse-triggered flip-flops are widely used in microprocessors in recent years due to their high performances. A great deal of research in design of pulsed flip-flops has been done in the last several decades. However, there is still much to be done to the design of low power and high performance pulsed flip-flops. The goal of this work is to provide a comprehensive study of low-power and high performance pulsed flip-flops.In this thesis, firstly, a general structure and design method for binary pulsed flip-flops are proposed, and several kinds of binary pulsed flip-flops are presented based on the proposed structrure and method. Variable supply voltage-clustered voltage scaling (VS-CVS) scheme can be very effective in reducing power consumption of CMOS circuits without losing system performance. In the thesis, a new design of low power and high performance pulsed level converting flip-flop is proposed, which is suitable for level conversion in critical paths in VS-CVS design. Lowering voltage swing and frequency of clock signal can lower power consumption effectively. A novel low clock swing double ede-triggered pulsed flip-flop is presented. With process scaling, leakage current power becomes innegitable. We propose a low power pulsed flip-flop based on MTCMOS. Finally, we extend the design of binary pulsed flip-flops to the design of ternary pulsed flip-flops. A general structure and design method for ternary pulsed flip-flops are proposed, and several kinds of ternary pulsed flip-flops are presented based on the proposed structrure and method.The design examples demonstrate that the proposed binary and ternary structure and design methods for pulsed flip-flops are practical, feasible and advanced. All the proposed low power flip-flops are simulated by HSPICE and the simulation results show that the proposed flip-flops have correct logic function and have simple structrure, and lower power consumption, smaller delay and PDP as compared to the conventional flip-flops. The proposed pulsed flip-flops can be used in low-power or high-speed VLSI designs. And the proposed low power and high performance level converting pulsed flip-flop is suited for lever conversion in critical paths in multiple-supply voltage designs.