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The Design And Implementation Of 16 Bits 500 MSPS Current-Steering D/A Converter Based On CMOS Technology

Posted on:2018-12-06Degree:MasterType:Thesis
Country:ChinaCandidate:P RenFull Text:PDF
GTID:2348330569986530Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
Digital-to-Analog Converter(DAC)plays a important role in realizing the conversion from digital signal to analog signal.As a key interface of electronic circuit,it has a tremendous development potential and market space in the high speed digital circuit and analog circuit with high precision.Due to the limitation of the process and technique,there are still many performance deficiencies,so the research and design of DAC,especially for the design and research of DAC with high speed and high precision have greatly significant.After compared different structure and performance of DAC,the 5+4+7segmented current steering DAC is adopted which has advantages in speed,area,power,consumption and complexity and can reach optimum combination of thermometer coding and binary encoded.It is also conducive to achieve the performance total of 16 bits 500 MSPS DAC.In order to meet the design index and optimize the performance of the circuit,the design of the bandgap voltage reference can provide accurate and stable reference voltage for current sources to improve the dynamic performance of current steering DAC;In order to ensure the switch control signals are simultaneous and reduce the crosspoint of the switch control signals,a synchronized and low crosspoint switch drive circuit is designed.In order to improve mismatch of current sources,designing the fuse trimming circuit by trimming the output current of current sources can greatly improve the current steering DAC linearity.Based on 0.18?m CMOS process,the system of DAC is pre-simulation under Cadence Spectre software,the simulation shows that: when the sampling frequency is500 MHz and the input signal frequency is 102 MHz,setting time is 10.28 ns,Spurious Free Dynamic Range is 82.16 dBc.Results prove that the design achieves the expected goal and meets the design requirements.For the design of the fuse trimming circuit,the measured DNL and INL are-0.72LSB~9.07 LSB and-5.55LSB~18.1LSBbefore the fuse trimming,respectively and they are-3.95LSB~0.70 LSB and-1.94LSB~8.06 LSB after the fuse trimming,respectively;The test results prove that the fuse trimming circuit can greatly improve linearity of the current steering DAC.
Keywords/Search Tags:DAC, segmented current steering, Fuse Trimming, SFDR
PDF Full Text Request
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