The Research And Application Of Flip-flops Based On Reducing Leakage-power

In 1965, Intel co-founder Gordon E. Moore predicted that the development pattern of IC industry: density of integrated circuits increased quadruple every three years and feature sizes shrink times every three years. The development of integrated circuit sizes from 180nm, 130nm, gradually over to 90nm, 65nm and 45nm [1-5]. As feature sizes continue to decrease, threshold voltage and other parameters of the transistor scale down, resulting in leakage power increasing.The leakage power consumption in the proportion of the total power consumption is increasing. However, the previous researchers concerned how to reduce the chip's dynamic power. Currently, in the chip background of the urgent that needs to reduce leakage power consumption, designers have done a more detailed study to the leakage power, and have proposed a variety of leakage power reduction technique, such as multi-threshold technology and the transistor stack technology. This paper focuses on the basic unit of sequential circuits—flip-flops,to investigate methods of reducing leakage power consumption of IC under the deep sub-micron process. The main contents of this paper are shown as follows:First, The paper studies three kinds of leakages majorly: sub-threshold leakage current, gate leakage current and drain-source - substrate junction reverse bias current and detail their mechanism under the deep sub-micron process. As the leakage current increases, leakage power reduction technique evolves. The paper analyzes the existing leakage power reduction technique of the traditional CMOS circuit. Leakage power reduction technique consists of two kinds: activity one and sleep one. The former includes the transistor stack and the P-type circuit design technology, and the latter mainly refers to multi-threshold technology, etc.Second, the innovations of this paper focus on leakage power reduction technique research of the energy recovery sequential circuits. Therefore, the work principle of several energy recovery logic circuit and flip-flop structure are discussed. And a variety of activity leakage power reduction technical are carried out for design optimization of the triggers, designed circuits are tested in the sequential system. The activity leakage power measurement of the circuit, gate-length biasing technique and P-type design technology of the energy recovery sequential circuit are discussed. This paper selects two typical logic circuits, CPAL and ECRL to explore and research gate-length biasing technique and P-type design technology used for adiabatic circuits, and results show that the total power and leakage power consumption have been reduced effectivly.Finally, the application of the sleep leakage power reduction in sequential circuits is analyzed. Taken as an example, flip-flops based on two-phase CPAL using power-gating scheme and MTCMOS are teseted, and the energy consumption can be saved greatly.