Design Of Low-power Pulsed-triggered Flip-flops Based On CMOS Process

With the advances of CMOS process, the integration level and clock frequency of integrated circuits are increased, leading to high power density. Huge power dissipation not only degrades the reliability of circuits and boosts packaging and cooling costs, but also weakens the endurance capacity of portable electronic devices. Thus, the low-power design becomes a prominent issue for high-performance integrated circuits.The clock system accounts for 30% to 60% of the total power in digital VLSI circuits. The clock system includes clock distribution network and flip-flops, and 90% of its power is consumed by the flip-flops and the last branches of the clock distribution network that drives the flip-flops. Flip-flops are basic sequential elements and they have a deep impact on power consumption, delay, area and signal integrity in digital integrated circuits. These factors make the low-power and high-performance flip-flops become the research focus in digital integrated circuits.Compared with traditional master-slave flip-flops, pulse-triggered flip-flops are characterized by simpler structure, smaller D-to-Q delay and soft edge, so they are widely used in modern microprocessors. The goal of this thesis is to design low-power pulse-triggered flip-flops. Firstly, two novel low-power pulse generators N-PG1 and N-PG2 for explicit-pulse triggered flip-flops are proposed, and a high-speed and low-power explicit-pulsed dual-edge triggered flip-flop (SEDNIFF) is also proposed to meet the high performance of critical paths. The proposed N-PG1 and N-PG2 reduce short-circuit current by well controlling the charge and discharge paths of their internal nodes, so the power consumption is decreased. Moreover, N-PG2 has more balanced delay time of pulse generating on both clock edges, helping to reduce the minimum D-Q delay of the pulse-triggered flip-flop. The proposed SEDNIFF sets the latch node inside its structure, so that the latch is simplified and the impact with output load variation is reduced. As a result, this new flip-flop is characterized by low power and small delay. Secondly, an explicit-pulsed dual-edge triggered level converting flip-flop with a transmission gate (LCFF-TG) is proposed, acting as the level-shifting circuit at the interface in dual-supply circuits. This new LCFF inserts a pulse-controlled transmission gate in the cross coupled inverters to reduce the race current during the sampling period, so the total power consumption is decreased. Finally, in order to gain further improvements in power consumption, a conditional clock technique based on clock triggering edge control technique is proposed, which draws the advantages of conditional discharge technique and clock gating technique. Furthermore, a conditional clock pulse-triggered flip-flop (CCFF) based on this technique is proposed. The proposed CCFF can block its clock when the input remains unchanged, so the redundant transitions at internal nodes are eliminated and considerable power savings are achieved.Each design in this thesis includes both front-end design and back-end design. The proposed novel pulse-triggered flip-flops are proved to be advanced and practical. Based on the TSMC0.18μm technology, the postlayout simulation results show that all the proposed low-power pulse-triggered flip-flops have ideal logic functionality. Compared with homogeneous pulse-triggered flip-fops in published papers, the proposed SEDNIFF has the lowest power dissipation under different input switching activities, and it has 7.0%～17.0% reduction in power dissipation and 12.2%～23.5% reduction in PDP when the input switching activity is 25%, which is suitable for using in low-power and low-delay critical paths. Compared with homogeneous pulse-triggered level converting flip-flops, the novel LCFF-TG has the lowest power dissipation under different input switching activities, and it has 15.8%～57.3% reduction in power dissipation and 6.8%～60.1% reduction in PDP when the input switching activity is 25%, which is suitable for using in high-performance dual-supply circuits. The proposed CCFF has lower power dissipation than other homogeneous pulse-triggered flip-flops when the input switching activity is below 50%, who gains an improvement of 49.6%～61.6% in power dissipation when the input switching activity is 10%. However, the D-to-Q delay of CCFF is increased due to conditional clock technique, so it is suitable for using in low-power non-critical paths which are not sensitive to delay.