Research On Low Power Flip-flops Design

One of the significant components of low power VLSI design is how to reduce the clock related power. Some researches show that the clock system consumes 20%-50% of the total chip power. In this clock system power, 90% is consumed by the flip-flops themselves. So it is very important in total power saving by reducing flip-flop power consumption.Dynamic power is dominant component of the average power dissipation in CMOS circuits. And the value of dynamic power is determined by node capacitance, supply voltage, clock frequency and switching activity of CMOS circuits. So most low power designs are achieved by reducing one or more those above parameters. In this paper, low power flip-flops designs by the reduction of the load of clock or the data path; by the reduction of clock swing; by the reduction of clock frequency and by the reduction of those idle transitions in CMOS circuits with clock gating are discussed. Furthermore, low power flip-flop design by reducing the short-circuit power which relates with clock overlapping is also mentioned in this paper.