Research Of Energy-efficient Flip-flops For Low-power Mobile SoC Applications

The dramatic advances of mobile electronic equipment are attributed to the constant scaling of semiconductor process,which lead to enhanced integration density and high clock frequency.However,the consequently increased power consumption causes higher chip temperature,thereby producing significant challenges for performance,yield,cooling,and packaging of integrated circuits.Therefore,power reduction has become increasingly challenging with the miniaturization of transistors.Flip-flops are the fundamental synchronous logic components in microprocessors.Typically,Flip-flops consume a significant portion of power consumption in an SoC chip.Therefore,low power FFs with competitive speed performance are highly desirable for green computing and the proliferation of portable electronics.To satisfy the market requirement of the boosting performance and functionality of the portable electronic equipment and reduce the power consumption of flip-flops,this paper concentrates on the low-power master-slave single-phase-clocked flip-flops.For achieving power reduction,we firstly investigated the design techniques and challenges of the previously published low-power flip-flops.To solve these challenges,we conclude three design techniques,naming the conditional charging,logic recombination,and topology compression.Then,based on single-phase-clocked technique,three innovative and low-power flip-flops are proposed:Single-phase-clocked redundant-transition-free flip-flop(SRFF),Energy-efficient SRFF(ESRFF),and(Static Clocked-Driven-Transistor Compression Flip-Flop,SC~2FF).SRFF is firstly proposed in this paper for achieving high energy efficiency for low power applications.The conditional charging technique is employed in the proposed SRFF to eliminate the redundant transitions at internal nodes when the input data D is maintained at the same logic level for consecutive clock cycles.ESRFF is proposed for reducing the propagation delay and the power consumption of SRFF.The logically equivalent transistors are compressed to in the novel ESRFF,therefore reduces the clock load and the power consumption.Besides,the conditional charging circuitry is embedded to the critical propagation path to enhance the speed performance.Finally,a novel SC~2FF with topologically compressed transistors is proposed for providing low dynamic and leakage power consumption.Since the data switching activity of clock signal is always one,the clock-driven-transistors with equivalent logic function are merged to reduce the clock load and dynamic power consumption.The proposed flip-flops provide the lower power consumption while maintaining similar speed performance as compared to the previously published flip-flops.The previously published flip-flops and the proposed three novel single-phase-clocked flip-flops are compared with TSMC 40nm LP technology.The dynamic power consumption is evaluated assuming that all the FFs operate at a typical?value of 20%and provide similar speed performance.The dynamic power of the proposed SRFF is suppressed by up to 27.87%as compared to the previously published low power flip-flops.The dynamic power of the ESRFF is reduced by 22.89%as compared to the new SRFF.Moreover,the novel SC~2FF lowers the dynamic power by up to 56.14%as compared to the previously published flip-flops as well as the proposed SRFF and ESRFF.Furthermore,up to 56.14%reduction of leakage power consumption is achieved by the proposed SC~2FF as compared to the previously published flip-flops.