The Design And Application Of Energy-efficient Flip-flops

Since the integrated circuit technology is developing rapidly,the size of transistors in the circuit is constantly reduced,the frequency and integration of the circuit will be promoted.The high circuit frequency lead to difficulties of timing convergence,as the same,the high integration of a circuit brings a high power density,power consumption issues have become increasingly prominent.As flip-flops is the most basic cell in the integrated circuit,the clock frequency of the chip is largely determined by the speed of the flip-flops,and the power consumption of the flip-flops can be accounted for 30%-50% of the entire chip.So it becomes more and more important to design energy-efficient flip-flops with better timing and power consumption.In this paper,the full custom research of energy-efficient flip-flops is carried out under the 40 nm process,using the CMOS structure.In order to help the key components in the FT-MX chip to achieve timing convergence and reduce power consumption.The main work and innovation include the following aspects:1)In this paper,we analyze the structure and performance of the traditional transmission gate master-slave flip flops,and use it as the contrast object for proposed flip-flops in the worst coner(0.81 V,125 C).Then,aiming at the problem of slow speed of traditional flip-flop,a new type of high speed pulse latch flip-flop is proposed,which has a negative setup time and improves the performance by 48.9%.In order to reduce power consumption,two kinds of low power flip-flops are designed.Among them,the single phase clock flip-flop has improved the circuit structure compared to the traditional one,which has a better power consumption performance in the case of severe data flip,and the EDP is improved by 27.8%.The other kind of flip-flop has pseudo single phase clock structure.It uses a pseudo single phase clock structure and a new type of structure.The EDP is improved by 29.2% compared with the traditional master-slave flip-flop.2)In order to satisfy the needs of practical engineering,this paper design the proposed three kinds of energy-efficient flip-flops for testability.Then we put scanning structure into them.Finally,on the basis of the design,we propose three energy efficient flip-flops with asynchronous reset function and one with synchronous reset function.3)we apply the energy-efficient flip-flops into the physical design of the FT-MX chip.The energy-efficient flip-flops are used to replace the traditional master-slave flip-flop,in order to help improve the performance and power consumption of certain parts of the chip.In this paper,the pulse latch flip-flop is used in the critical path of the DMA module,because the path's timing is difficult to converge,finally,it helps the path to achieve the goal of time sequence convergence.Two low power flip flops are then used in the FFT accelerator,the power consumption is reduced by 24% and 28.1%,and the density and area are also improved.In addition,this paper proposes a 16 bit flip-flop,which is made up with pulse-latch flip-flops.It is used in the register file's bypass array,to help the register file to achieve timing convergence and achieve the frequency goal of 1GHZ.